Recent developments in semiconductor processing technologies and memory cell technologies have continued to increase the density achieved in integrated circuit memory arrays. For example, certain passive element memory cell arrays may be fabricated having word lines approaching the minimum feature size (F) and minimum feature spacing for the particular word line interconnect layer, and also having bit lines approaching the minimum feature width and minimum feature spacing for the particular bit line interconnect layer. Moreover, three-dimensional memory arrays having more than one plane or level of memory cells have been fabricated implementing such so-called 4F2 memory cells on each memory plane. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication,” and in U.S. Pat. No. 5,835,396 to Zhang, entitled “Three-Dimensional Read-Only Memory.”
A variety of other memory cell technologies and arrangements are also known. For example, NAND flash and NROM flash EEPROM memory arrays are known to achieve relatively small memory cells. Other small flash EEPROM cells are known which use hot electron programming, such as NROM and floating gate NOR flash memory arrays. Such memory cells may also be desirable for a 3D memory array, although they frequently use many masks to produce a memory layer, and some use relatively high programming currents. Yet other memory cell technologies include Dynamic Random Access Memory (DRAM) type of memory cells, and Ferro-electric (FeRAM) memory cells.
A three-dimensional (3D) memory array is most efficient when the number of cell on each bit line and word line is large. This number of cells is frequently called the fan-out (N) of the bit line and the word line. A large fan-out reduces the number of vertical connections between the array lines on each memory layer and the circuitry below. These vertical connections cannot lie beneath the individual memory cells on each layer, and thus may add significantly to the chip area. But a large fan-out frequently has certain electrical disadvantages depending on the memory cell technology being used. For example, the capacitance of array lines and the resistance of array lines may increase by the fan-out (N) factor, and leakage per cell may cause power dissipation to increase by a factor of N2. Of particular interest, a large fan-out EEPROM array causes interaction between all the cells within a range defined by the fan-out of the bit line and the fan-out of the word line. This interaction is detrimental for EEPROM arrays because it causes a partial, but cumulative, disturb of some bits while reading or writing other bits. It also defines the so-called erase block size, since all the cells in an interacting group are erased at the same time. The memory cells which are disturbed during writing are those that are “half-selected” cells, which are memory cells that are connected to either the currently selected word line or the currently selected bit line, but not both. Because the number of half-selected cells increases with increasing fan-out, and because the amount a cell is disturbed is a cumulative effect of a great number of cycles (which varies with fan out proportional to N2), the data in those cells could easily be destroyed if the array line fan-outs were large. As a result, 3D memory arrays must make a fan-out trade-off between electrical requirements and layout efficiency that is particularly detrimental in 3D EEPROM arrays.
Many two-dimensional (2D) memory arrays (i.e., having only a single memory plane) segment the memory array lines and connect the segments to longer lines. Examples include Flash EEPROM devices, which segment the bit lines, DRAMs which segment the word line and sometimes the bit line, and SRAMs which segment the word line. Such devices have the segment switches on one layer (e.g., within the silicon substrate), and have a different layer for memory cells with segmented lines, and one layer of long lines (e.g., global lines). Despite such progress, memory arrays having even greater density are desirable. In particular, a memory array configuration more easily fashioned into a three-dimensional memory array is highly desired.